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ZL38001 AEC for Analog Hands-Free Communication
Data Sheet
Zarlink has introduced a new generation family of AEC (ZL38002 and ZL38004). Zarlink recommends these products for new designs.
October 2006
Features
* * * * * * * * * * * Contains two echo cancellers: 112 ms acoustic echo canceller + 16 ms line echo canceller Works with low cost voice codec. ITU-T G.711 or signed mag /A-Law, or linear 2's comp Each port may operate in different format Advanced NLP design - full duplex speech with no switched loss on audio paths Fast re-convergence time: tracks changing echo environment quickly Adaptation algorithm converges even during Double-Talk Designed for exceptional performance in high background noise environments Provides protection against narrow-band signal divergence Howling prevention stops uncontrolled oscillation in high loop gain conditions Offset nulling of all PCM channels Serial micro-controller interface
ZL38001DGA ZL38001QDC ZL38001QDG1 ZL38001DGF1 ZL38001DGE1
Ordering Information 36 Pin QSOP Tubes 48 Pin TQFP Trays 48 Pin TQFP* Trays, Bake & Drypack 36 Pin SSOP* Tape & Reel, Bake & Drypack 36 Pin SSOP* Tubes, Bake & Drypack *Pb Free Matte Tin -40C to +85C
* * * * * * * * * *
ST-BUS, GCI, or variable-rate SSI PCM interfaces User gain control provided for speaker path (-24 dB to +48 dB in 3 dB steps) 18 dB gain at Sout to compensate for high ERL environments AGC on speaker path Handles up to 0 dB acoustic echo return loss Transparent data transfer and mute options 20 MHz master clock operation Low power mode during PCM Bypass Bootloadable for future factory software upgrades 2.7 V to 3.6 V supply voltage; 5 V-tolerant inputs
Sin MD1
/A-Law/
Linear
Offset Null
+
Limiter
+
S2
ADV NLP Program RAM S3 Program ROM
18dB Gain
Linear/ /A-Law
Sout DATA1
ACOUSTIC ECHO PATH
NBSD
S1
Micro Interface
DATA2
CONTROL UNIT Adaptive Filter Double Talk Detector
R3 R2 ADV NLP
Line ECho Path
PORT 1
PORT 2
Adaptive Filter NBSD
Howling Controller
R1
MD2 Rout Linear/ /A-Law
Limiter
SCLK
-24 -> +21 dB
AGC
User Gain
-
CS
+
+
Offset Null
/A-Law/
Linear
Rin
VDD
VSS
RESET
FORMAT
ENA2
ENA1
LAW
F0i
BCLK/C4i
MCLK
Figure 1 - Functional Block Diagram 1
Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2004-2006, Zarlink Semiconductor Inc. All Rights Reserved.
ZL38001
Applications
* Hands-free in automobile applications
MT93L16 Description AEC for analog handsfree communication Application Analog Desktop phone Analog Intercom Features AEC LEC Gains Noise Reduction Integrated Codecs 1 channel 1 channel User Gain N N 1 channel 1 channel User Gain/18 dB Gain on Sout N N 1 channel Custom Load User Gain + System tuning gains Y N ZL38001 ZL38002
Data Sheet
ZL38003 AEC with noise reduction & codecs for digital hands-free communication
AEC for analog hands- AEC with noise reduction for digital free communication hands-free communication
Analog Desktop phone Hands-free Car Kits Hands-free Car Kits Analog Intercom Digital Desktop Phone Home Security Digital Desktop Phone Home Security Intercom & Pedestals Intercom & Pedestals
1 channel Custom Load User Gain + System tuning gains Y dual channel
Table 1 - Acoustic Echo Cancellation Family
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ZL38001
Data Sheet
Figure 2 - Pin Connections Pin Description QSOP Pin # 1 TQFP Pin # 43 Name ENA1 Description SSI Enable Strobe/ST-BUS & GCI Mode for Rin/Sout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this strobe must be present for frame synchronization. This is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer for on Rin/Sout pins. Strobe period is 125 microseconds. For ST-BUS or GCI, this pin, in conjunction with the MD1 pin, selects the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Rin/Sout (Input). When in ST-BUS or GCI operation, this pin, in conjunction with the ENA1 pin, will select the proper mode for Rin/Sout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode. SSI Enable Strobe /ST-BUS & GCI Mode for Sin/Rout (Input). This pin has dual functions depending on whether SSI or ST-BUS/GCI is selected. For SSI, this is an active high channel enable strobe, 8 or 16 data bits wide, enabling serial PCM data transfer on Sin/Rout pins. Strobe period is 125 microseconds. For ST-BUS/GCI, this pin, in conjunction with the MD2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). ST-BUS & GCI Mode for Sin/Rout (Input). When in ST-BUS or GCI operation, this pin in conjunction with the ENA2 pin, selects the proper mode for Sin/Rout pins (see ST-BUS and GCI Operation description). Connect this pin to Vss in SSI mode.
2
45
MD1
3
46
ENA2
4
47
MD2
3
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IC IC IC LAW NC FORMAT NC
MCLK
ENA1 MD1 ENA2 MD2 Rin Sin IC MCLK IC IC IC LAW FORMAT RESET NC NC SCLK CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
QSOP
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
IC IC IC MCLK2 NC VSS VDD2
VSS2
IC IC BCLK/C4i F0i Rout Sout VDD NC DATA1 DATA2
NC MCLK2 IC IC IC NC ENA1 NC MD1 ENA2 MD2 Rin
36 38 40
NC VSS VDD2 VSS2 NC IC IC BCLK/C4i NC F0i Rout NC 34 32 30 28 26 24 22 20 42 44 16 46 14 48 2 4 6 8 10 12
TQFP
18
Sout VDD NC DATA1 NC DATA2 NC CS SCLK NC NC RESETB
NC Sin IC NC
ZL38001
Pin Description (continued) QSOP Pin # 5 TQFP Pin # 48 Name Rin Description
Data Sheet
Receive PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2's complement linear format. This is the Receive Input channel from the line (or network) side. Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Send PCM Signal Input (Input). 128 kbps to 4096 kbps serial PCM input stream. Data may be in either companded or 2's complement linear format. This is the Send Input channel (from the microphone). Data bits are clocked in following SSI, GCI or ST-BUS timing requirements. Internal Connection (Input). Must be tied to Vss. Master Clock (Input). Nominal 20 MHz Master Clock input (may be asynchronous relative to 8 KHz frame signal.) Tie together with MCLK2 (pin 33). Internal Connection (Input). Must be tied to Vss. A/ Law Select (Input). When low, selects -Law companded PCM. When high, selects A-Law companded PCM. This control is for both serial pcm ports.
6
2
Sin
7 8
3 5
IC MCLK
9,10,11 12
6, 7, 8 9
IC LAW
13
11
FORMAT ITU-T/Sign Mag (Input). When low, selects sign-magnitude PCM code. When high, selects ITU-T (G.711) PCM code. This control is for both serial pcm ports. RESET SCLK CS DATA2 Reset / Power-down (Input). An active low resets the device and puts the ZL38001 into a low-power stand-by mode. Serial Port Synchronous Clock (Input). Data clock for the serial microport interface. Serial Port Chip Select (Input). Enables serial microport interface data transfers. Active low. Serial Data Receive (Input). In Motorola/National serial microport operation, the DATA2 pin is used for receiving data. In Intel serial microport operation, the DATA2 pin is not used and must be tied to Vss or Vdd. Serial Data Port (Bidirectional). In Motorola/National serial microport operation, the DATA1 pin is used for transmitting data. In Intel serial microport operation, the DATA1 pin is used for transmitting and receiving data. Positive Power Supply (Input). Nominally 3.3 volts. Send PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2's complement linear PCM format. This is the Send Out signal after acoustic echo cancellation and non-linear processing. Data bits are clocked out following SSI, STBUS or GCI timing requirements. Receive PCM Signal Output (Output). 128 kbps to 4096 kbps serial PCM output stream. Data may be in either companded or 2's complement linear PCM format. This is the Receive out signal after line echo cancellation nonlinear processing, AGC and gain control. Data bits are clocked out following SSI, ST-BUS or GCI timing requirements.
14 17 18 19
13 16 17 19
20
21
DATA1
22 23
23 24
VDD Sout
24
26
Rout
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ZL38001
Pin Description (continued) QSOP Pin # 25 TQFP Pin # 27 Name F0i Description
Data Sheet
Frame Pulse (Input). In ST-BUS (or GCI) operation, this is an active-low (or active-high) frame alignment pulse, respectively. SSI operation is enabled by connecting this pin to Vss.
26
29
BCLK/C4i Bit Clock/ST-BUS Clock (Input). In SSI operation, BCLK pin is a 128 kHz to 4.096 MHz bit clock. This clock must be synchronous with ENA1 and ENA2 enable strobes. In ST-BUS or GCI operation, C4i pin must be connected to the 4.096 MHz (C4) system clock. IC VSS2 VDD2 VSS MCLK2 IC NC Internal Connection (Input). Tie to Vss. Digital Ground (Input). Nominally 0 volts. Positive Power Supply (Input). Nominally 3.3 volts (tie together with VDD, pin 22). Digital Ground (Input). Nominally 0 volts (tie together with VSS2, pin 29). Master Clock (Input). Nominal 20 MHz master clock (tie together with MCLK, pin 8). Internal Connection (Input). Tie to Vss. No Connect (Output). This pin should be left unconnected.
27, 28 29 30 31 33
34,35,36
30, 31 33 34 35 38 39, 40, 41 1, 4, 10, 12, 14, 15, 18, 20, 22, 25, 28, 32, 36, 37, 42, 44
15, 16, 21, 32
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ZL38001 Table of Contents
Data Sheet
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 Adaptation Speed Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2 Advanced Non-Linear Processor (ADV-NLP)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3 Narrow Band Signal Detector (NBSD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.4 Howling Detector (HWLD)1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.5 Offset Null Filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.6 Limiters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.7 User Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.8 AGC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.9 18 dB Gain Pad at Sout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.10 Mute Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.11 Bypass Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.12 Adaptation Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.13 ZL38001 Throughput Delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.14 Power Down / Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 PCM Data I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 ST-BUS and GCI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.2 SSI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 PCM Law and Format Control (LAW, FORMAT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.4 Linear PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.5 Bit Clock (BCLK/C4i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 Master Clock (MCLK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0 Microport . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1 Bootload Process and Execution from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.0 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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ZL38001 List of Figures
Data Sheet
Figure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1) . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2) . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3) . . . . . . . . . . . . . . . . . . 16 Figure 6 - ST-BUS and GCI 16-Bit 2's Complement Linear PCM I/O (Mode 4). . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 7 - SSI Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 8 - Serial Microport Timing for Intel Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 10 - Master Clock - MCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Figure 11 - GCI Data Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 12 - ST-BUS Data Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 13 - SSI Data Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 14 - INTEL Serial Microport Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 15 - Motorola Serial Microport Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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ZL38001 List of Tables
Data Sheet
Table 1 - Acoustic Echo Cancellation Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Table 2 - Quiet PCM Code Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 3 - ST-BUS & GCI Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4 - SSI Enable Strobe Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5 - Companded PCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table 6 - Bootload RAM Control (BRC) Register States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table 7 - Reference Level Definition for Timing Measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
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Zarlink Semiconductor Inc.
ZL38001 List of Register Tables
Data Sheet
Register Table 1 - Main Control Register (MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register Table 2 - Acoustic Echo Canceller Control Register (AEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Register Table 3 - Line Echo Canceller Control Register (LEC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Register Table 4 - Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register) . . . . . . . . . . . . . . . . . 32 Register Table 5 - Line Echo Canceller Status Register (LSR) (* Do not write to this register) . . . . . . . . . . . . . . . . . . . . . 33 Register Table 6 - Receive Gain Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Register Table 9 - Double Talk detection Threshold Register (DTDT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Register Table 11 - Receive (Rin) Peak Detect Register 2 (RIPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Register Table 12 - Receive (Rin) ERROR Peak Detect Register 1 (REPD1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Register Table 13 - Receive (Rin) ERROR Peak Detect Register 2 (REPD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Register Table 14 - Receive (Rout) Peak Detect Register 1 (ROPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Register Table 22 - Rout Limiter Register 1 (RL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Register Table 23 - Rout Limiter Register 2 (RL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register Table 24 - Sout Limiter Register (SL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Register Table 25 - Firmware Revision Code Register (FRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Register Table 26 - Bootload RAM Control Register (BRC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Register Table 27 - Bootload RAM Signature Register (SIG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
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Zarlink Semiconductor Inc.
ZL38001
1.0 Changes Summary
Data Sheet
The following table captures the changes from the November 2005 issue. Page 1 Item Change Updated Ordering Information
The following table captures the changes from the June 2004 issue. Page 1 1 Item Features Figure 1 - Functional Block Diagram Change Added 16 ms line echo canceller. Added line echo cancellor block.
2.0
Functional Description
The ZL38001 device contains an acoustic echo cancellers, as well as the many control functions necessary to operate the echo canceller. The ZL38001 provides clear signal transmission in both audio path directions to ensure reliable voice communication, even with low level signals. The ZL38001 does not use variable attenuators during double-talk or single-talk periods of speech, as do many other acoustic echo cancellers for speakerphones. Instead, the ZL38001 provides high performance full-duplex operation similar to network echo cancellers, so that users experience clear speech and uninterrupted background signals during the conversation. This prevents subjective sound quality problems associated with "noise gating" or "noise contrasting". The ZL38001 uses an advanced adaptive filter algorithm that is double-talk stable, which means that convergence takes place even while both parties are talking1. This algorithm allows continual tracking of changes in the echo path, regardless of double-talk, as long as a reference signal is available for the echo canceller. The echo tail cancellation capability of the acoustic echo canceller has been sized appropriately (112 ms) to cancel echo in an average sized office with a reverberation time of less than 112 ms. In addition to the echo cancellers, the following functions are supported: * * * * * * * * * Control of adaptive filter convergence speed during periods of double-talk, far end single-talk and near-end echo path changes Control of Non-Linear Processor thresholds for suppression of residual non-linear echo Howling detector to identify when instability is starting to occur and to take action to prevent oscillation Narrow-Band Detector for preventing adaptive filter divergence caused by narrow-band signals Offset Nulling filters for removal of DC components in PCM channels Limiters that introduce controlled saturation levels Serial controller interface compatible with Motorola, National and Intel microcontrollers PCM encoder/decoder compatible with /A-Law ITU-T G.711, /A-Law Sign-Mag or linear 2's complement coding Automatic gain control on the receive speaker path
1. Patent pending.
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Zarlink Semiconductor Inc.
ZL38001
2.1 Adaptation Speed Control
Data Sheet
The adaptation speed of the acoustic echo canceller is designed to optimize the convergence speed versus divergence caused by interfering near-end signals. Adaptation speed algorithm takes into account many different factors such as relative double-talk condition, far end signal power, echo path change and noise levels to achieve fast convergence.
2.2
Advanced Non-Linear Processor (ADV-NLP)1
After echo cancellation, there is likely to be residual echo which needs to be removed so that it will not be audible. The ZL38001 uses an NLP to remove low level residual echo signals which are not comprised of background noise. The operation of the NLP depends upon a dynamic activation threshold, as well as a double-talk detector which disables the NLP during double-talk periods. The ZL38001 keeps the perceived noise level constant, without the need for any variable attenuators or gain switching that causes audible "noise gating". The noise level is constant and identical to the original background noise even when the NLP is activated. The NLP can be disabled by setting the NLP- bit to 1 in the AEC control registers.
2.3
Narrow Band Signal Detector (NBSD)1
Single or multi-frequency tones (e.g., DTMF or signalling tones) present in the reference input of an echo canceller for a prolonged period of time may cause the adaptive filter to diverge. The Narrow Band Signal Detector (NBSD) is designed to prevent this divergence by detecting single or multi-tones of arbitrary frequency, phase, and amplitude. When narrow band signals are detected, the filter adaptation process is stopped but the echo canceller continues to cancel echo. The NBSD can be disabled by setting the NB- bit to 1 in the MC control registers.
2.4
Howling Detector (HWLD)1
The Howling detector is part of an Anti-Howling control, designed to prevent oscillation as a result of positive feedback in the audio paths. The HWLD can be disabled by setting the AH- bit to 1 in the (MC) control register.
2.5
Offset Null Filter
To ensure robust performance of the adaptive filters at all times, any DC offset that may be present on either the Rin signal or the Sin signal, is removed by highpass filters. These filters have a corner frequency placed at 40 Hz. The offset null filters can be disabled by setting the HPF- bit to 1 in the AEC control registers.
2.6
Limiters
To prevent clipping in the echo paths, two limiters with variable thresholds are provided at the outputs. The Rout limiter threshold is in Rout Limiter Register 1 and 2. The Sout limiter threshold is in Sout Limiter Register. Both output limiters are always enabled.
2.7
User Gain
The user gain function provides the ability for users to adjust the audio gain in the receive path (speaker path). This gain is adjustable from -24 dB to +48 dB in 3 dB steps. It is important to use ONLY this user gain function to adjust
1. Patent Pending
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
the speaker volume. The user gain function in the ZL38001 is optimally placed between the two echo cancellers such that no reconvergence is necessary after gain changes. The gain can be accessed through Receive Gain Control Register.
2.8
AGC
The AGC function is provided to limit the volume in the speaker path. The gain of the speaker path is automatically reduced during the following conditions: * * * * When clipping of the receive signal occurs When initial convergence of the acoustic echo canceller detects unusually large echo return When howling is detected The AGC can be disabled by setting the AGC- bit to 1 in MC control register
2.9
18 dB Gain Pad at Sout
The purpose of the 18 dB gain pad is to improve the subjective quality in low ERL environments. The ZL38001 can cancel echo with a ERL as low as 0 dB (attenuation from Rout to Sin). In many hand free applications, the ERL can be low (or negative). This is due to both speaker and microphone gain setting. The speaker gain has to be set high enough for the speaker to be heard properly and the microphone gain needs to be set high enough to ensure sufficient signal is sent to the far end. If the ERL (Acoustic Attenuation - speaker gain - microphone gain) is greater than 0 dB, then the echo canceller cannot cancel echo. To overcome this limitation, the ZL38001 has a 18 dB gain pad at Sout. The microphone gain can be reduced by 18 dB to allow either the speaker gain and/or the acoustic coupling to be increased by a total of 18 dB allowing more flexibility in the design.
2.10
Mute Function
A pcm mute function is provided for independent control of the Receive and Send audio paths. Setting the MUTE_R or MUTE_S bit in the MC register, causes quiet code to be transmitted on the Rout or Sout paths respectively. Quiet code is defined according to the following table. LINEAR 16 bits 2's complement +Zero (quiet code) 0000h SIGN/ MAGNITUDE -Law A-Law 80h CCITT (G.711) -Law A-Law
FFh
D5h
Table 2 - Quiet PCM Code Assignment
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Zarlink Semiconductor Inc.
ZL38001
2.11 Bypass Control
Data Sheet
A PCM bypass function is provided to allow transparent transmission of pcm data through the ZL38001. When the bypass function is active, pcm data passes transparently from Rin to Rout and from Sin to Sout, with bit-wise integrity preserved. When the Bypass function is selected, most internal functions are powered down to provide low power consumption. The BYPASS control bit is located in the main control MC register.
2.12
Adaptation Enable/Disable
Adaptation control bits are located in the AEC and LEC control registers. When the ADAPT- bit is set to 1, the adaptive filter is frozen at the current state. In this state, the device continues to cancel echo with the current echo model. When the ADAPT- bit is set to 0, the adaptive filter is continually updated. This allows the echo canceller to adapt and track changes in the echo path. This is the normal operating state.
2.13
ZL38001 Throughput Delay
In all modes, voice channels always have 2 frames of delay. In ST-BUS/GCI operation, the D and C channels have a delay of one frame.
2.14
Power Down / Reset
Holding the RESET pin at logic low will keep the ZL38001 device in a power-down state. In this state all internal clocks are halted, and the DATA1, Sout and Rout pins are tristated. The user should hold the RESET pin low for at least 200 msec following power-up. This will insure that the device powers up in a proper state. Following any return of RESET to logic high, the user must wait for 8 complete 8 KHz frames prior to writing to the device registers. During this time, the initialization routines will execute and set the ZL38001 to default operation (program execution from ROM using default register values).
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Zarlink Semiconductor Inc.
ZL38001
3.0 PCM Data I/O
Data Sheet
The PCM data transfer for the ZL38001 is provided through two PCM ports. One port consists of Rin and Sout pins while the second port consists of Sin and Rout pins. The data are transferred through these ports according to either ST-BUS, GCI or SSI conventions and the device automatically detects the correct convention. The device determines the convention by monitoring the signal applied to the F0i pin. When a valid ST-BUS (active low) frame pulse is applied to the F0i pin, the ZL38001 will assume ST-BUS operation. When a valid GCI (active high) frame pulse is applied to the F0i pin, the device will assume GCI operation. If F0i is tied continuously to Vss, the device will assume SSI operation. Figures 11 to 13 show timing diagrams of these 3 PCM-interface operation conventions.
3.1
ST-BUS and GCI Operation
The ST-BUS PCM interface conforms to Zarlink's ST-BUS standard with an active-low frame pulse. Input data is clocked in by the rising edge of the bit clock (C4i) three-quarters of the way into the bitcell and output data bit boundaries (Rout, Sout) occur every second falling edge of the bit clock (see Figure 11.) The GCI PCM interface corresponds to the GCI standard commonly used in Europe with an active-high frame pulse. Input data is clocked in by the falling edge of the bit clock (C4i) three-quarters of the way into the bitcell and output data bit boundaries (Rout, Sout) occur every second rising edge of the bit clock (see Figure 12.) Either of these interfaces (STBUS or GCI) can be used to transport 8 bit companded PCM data (using one timeslot) or 16 bit 2's complement linear PCM data (using two timeslots). The MD1/ENA1 pins select the timeslot on the Rin/Sout port while the MD2/ENA2 pin selects the timeslot on the Sin/Rout port, as in Table 3. Figures 3 to 6 illustrate the timeslot allocation for each of these four modes.
C4i start of frame (stbus & GCI) F0i (ST-BUS) F0i (GCI) PORT1 Rin
0
1
2
3
4
B
76543210 EC
Sout PORT2 Sin
76 543210
76 543210 EC
Rout
76 543210
outputs = High impedance inputs = don't care
In ST-BUS/GCI Mode 1, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 0. Note that the user can configure PORT1 and PORT2 into different modes.
Figure 3 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 0 (Mode 1)
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Zarlink Semiconductor Inc.
ZL38001
C4i start of frame (stbus & GCI) F0i (ST-BUS)
Data Sheet
0
1
2
3
4
B
F0i (GCI) PORT1 Rin
76 543210 EC
Sout
76 543210
PORT2 Sin
76 543210 EC
Rout outputs = High impedance inputs = don't care
76 543210
In ST-BUS/GCI Mode 2, echo canceller I/O channels are assigned to ST-BUS/GCI timeslot 2. Note that the user can configure PORT1 and PORT2 into different modes.
Figure 4 - ST-BUS and GCI 8-Bit Companded PCM I/O on Timeslot 2 (Mode 2)
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Zarlink Semiconductor Inc.
ZL38001
C4i start of frame (stbus & GCI) F0i (ST-BUS)
Data Sheet
0
1
2
3
4
D
F0i (GCI) PORT1 Rin
C
B
765432107654321076543210 EC
Sout
765432107654321076543210
PORT2 Sin
765432107654321076543210 EC
Rout
765432107654321076543210
outputs = High impedance inputs = don't care indicates that an input channel is bypassed to an output channel
ST-BUS/GCI Mode 3 supports connection to 2 B+D devices where timeslots 0 and 1 transport D and C channels and echo canceller (EC) I/O channels are assigned to ST-BUS timeslot 2 (B). Both PORT1 and PORT2 must be configured in Mode 3.
Figure 5 - ST-BUS and GCI 8-Bit Companded PCM I/O with D and C channels (Mode 3)
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Zarlink Semiconductor Inc.
ZL38001
C4i start of frame (stbus & GCI) F0i (stbus)
Data Sheet
F0i (GCI) Rin PORT1 Sout
S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
Sin PORT2 Rout
S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0 EC S 1413 12 11 10 9 8 7 6 5 4 3 2 1 0
outputs = High impedance inputs = don't care
ST-BUS/GCI Mode 4 allows 16 bit 2's complement linear data to be transferred using ST-BUS/GCI I/O timing. Note that PORT1 and PORT2 need not necessarily both be in mode 4.
Figure 6 - ST-BUS and GCI 16-Bit 2's Complement Linear PCM I/O (Mode 4)
PORT1 Rin/Sout Enable Pins MD1 0 0 1 1 ENA1 0 1 0 1
ST-BUS/GCI Mode Selection
PORT2 Sin/Rout Enable Pins MD2 ENA2 0 1 0 1
Mode 1. 8 bit companded PCM I/O on timeslot 0 Mode 2. 8 bit companded PCM I/O on timeslot 2. Mode 3. 8 bit companded PCM I/O on timeslot 2. Includes D & C channel bypass in timeslots 0 & 1. Mode 4. 16-bit 2's complement linear PCM I/O on timeslots 0 & 1. Table 3 - ST-BUS & GCI Mode Select
0 0 1 1
3.2
SSI Operation
The SSI PCM interface consists of data input pins (Rin, Sin), data output pins (Sout, Rout), a variable rate bit clock (BCLK), and two enable pins (ENA1, ENA2) to provide strobes for data transfers. The active high enable may be either 8 or 16 BCLK cycles in duration. Automatic detection of the data type (8 bit companded or 16-bit 2's complement linear) is accomplished internally. The data type cannot change dynamically from one frame to the next.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
In SSI operation, the frame boundary is determined by the rising edge of the ENA1 enable strobe (see Figure 7). The other enable strobe (ENA2) is used for parsing input/output data and it must pulse within 125 microseconds of the rising edge of ENA1. In SSI operation, the enable strobes may be a mixed combination of 8 or 16 BCLK cycles allowing the flexibility to mix 2's complement linear data on one port (e.g., Rin/Sout) with companded data on the other port (e.g., Sin/Rout). Enable Strobe Pin ENA1 ENA2 Designated PCM I/O Port Line Side Echo Path (PORT 1) Acoustic Side Echo Path (PORT 2) Table 4 - SSI Enable Strobe Pins
3.3
PCM Law and Format Control (LAW, FORMAT)
The PCM companding/coding law used by the ZL38001 is controlled through the LAW and FORMAT pins. ITU-T G.711 companding curves for -Law and A-Law are selected by the LAW pin. PCM coding ITU-T G.711 and SignMagnitude are selected by the FORMAT pin. See Table 5.
BCLK start of frame (SSI)
PORT1 ENA1
Rin
8 or 16 bits
EC
Sout 8 or 16 bits
PORT2 ENA2
Sin
8 or 16 bits
EC
Rout outputs = High impedance inputs = don't care Note that the two ports are independent so that, for example, PORT1 can operate with 8-bit enable strobes and PORT2 can operate with 16-bit enable strobes. 8 or 16 bits
Figure 7 - SSI Operations
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Zarlink Semiconductor Inc.
ZL38001
Sign-Magnitude FORMAT=0 /A-LAW LAW = 0 or 1 + Full Scale + Zero - Zero - Full Scale 1111 1111 1000 0000 0000 0000 0111 1111 ITU-T (G.711) FORMAT=1 -LAW LAW = 0 1000 0000 1111 1111 0111 1111 0000 0000 A-LAW LAW =1 1010 1010 1101 0101 0101 0101 0010 1010
Data Sheet
PCM Code
Table 5 - Companded PCM
3.4
Linear PCM
The 16-bit 2's complement PCM linear coding permits a dynamic range beyond that which is specified in ITU-T G.711 for companded PCM. The echo-cancellation algorithm will accept 16-bits 2's complement linear code which gives a maximum signal level of +15 dBm0.
3.5
Bit Clock (BCLK/C4i)
The BCLK/C4i pin is used to clock the PCM data for GCI and ST-BUS (C4i) interfaces, as well as for the SSI (BCLK) interface. In SSI operation, the bit rate is determined by the BCLK frequency. This input must contain either eight or sixteen clock cycles within the valid enable strobe window. BCLK may be any rate between 128 KHz to 4.096 MHz and can be discontinuous outside of the enable strobe windows defined by ENA1, ENA2 pins. Incoming PCM data (Rin, Sin) are sampled on the falling edge of BCLK while outgoing PCM data (Sout, Rout) are clocked out on the rising edge of BCLK. See Figure 13. In ST-BUS and GCI operation, connect the system C4 (4.096 MHz) clock to the C4i pin.
3.6
Master Clock (MCLK)
A nominal 20 MHz, continuously-running master clock (MCLK) is required. MCLK may be asynchronous with the 8 KHz frame.
4.0
Microport
The serial microport provides access to all ZL38001 internal read and write registers, plus write-only access to the bootloadable program RAM (see next section for bootload description.) This microport is compatible with Intel MCS-51 (mode 0), Motorola SPI (CPOL=0, CPHA=0) and National Semiconductor Microwire specifications. The microport consists of a transmit/receive data pin (DATA1), a receive data pin (DATA2), a chip select pin (CS) and a synchronous data clock pin (SCLK). The ZL38001 automatically adjusts its internal timing and pin configuration to conform to Intel or Motorola/National requirements. The microport dynamically senses the state of the SCLK pin each time CS pin becomes active (i.e., high to low transition). If SCLK pin is high during CS activation, then Intel mode 0 timing is assumed. In this case DATA1 pin is defined as a bi-directional (transmit/receive) serial port and DATA2 is internally disconnected. If SCLK is low during CS activation, then Motorola/National timing is assumed and DATA1 is defined as the data transmit pin while DATA2 becomes the data receive pin. The ZL38001 supports Motorola half-duplex processor mode (CPOL=0
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
and CPHA=0). This means that during a write to the ZL38001, by the Motorola processor, output data from the DATA1 pin must be ignored. This also means that input data on the DATA2 pin is ignored by the ZL38001 during a valid read by the Motorola processor. All data transfers through the microport are two bytes long. This requires the transmission of a Command/Address byte followed by the data byte to be written to or read from the addressed register. CS must remain low for the duration of this two-byte transfer. As shown in Figures 8 and 9, the falling edge of CS indicates to the ZL38001 that a microport transfer is about to begin. The first 8 clock cycles of SCLK after the falling edge of CS are always used to receive the Command/Address byte from the microcontroller. The Command/Address byte contains information detailing whether the second byte transfer will be a read or a write operation and at what address. The next 8 clock cycles are used to transfer the data byte between the ZL38001 and the microcontroller. At the end of the two-byte transfer, CS is brought high again to terminate the session. The rising edge of CS will tri-state the DATA1 pin. The DATA1 pin will remain tri-stated as long as CS is high. Intel processors utilize Least Significant Bit (LSB) first transmission while Motorola/National processors use Most Significant Bit (MSB) first transmission. The ZL38001 microport automatically accommodates these two schemes for normal data bytes. However, to ensure timely decoding of the R/W and address information, the Command/Address byte is defined differently for Intel and Motorola/National operations. Refer to the relative timing diagrams of Figure 8 and Figure 9. Receive data bits are sampled on the rising edge of SCLK while transmit data is clocked out on the falling edge of SCLK. Detailed microport timing is shown in Figure 14 and Figure 15.
4.1
Bootload Process and Execution from RAM
A bootloadable program RAM (BRAM) is available on the ZL38001 to support factory-issued software upgrades to the built-in algorithm. To make use of this bootload feature, users must include 4096 X 8 bits of memory in their microcontroller system (i.e., external to the ZL38001), from which the ZL38001 can be bootloaded. Registers and program data are loaded into the ZL38001 in the same fashion via the serial microport. Both employ the same command / address / data byte specification described in the previous section on serial microport. Either intel or motorola mode may be transparently used for bootloading. There are also two registers relevant to bootloading (BRC=control and SIG=signature, see Register Summary). The effect of these register values on device operation is summarized in Table 6. Bootload mode is entered and exited by writing to the bootload bit in the Bootload RAM Control (BRC) register at address 3fh (see Register Summary). During bootload mode, any serial microport "write" (R/W command bit =0) to an address other than that of the BRC register will contribute to filling the program BRAM. Call these transactions "BRAM-fill" writes. Although a command/address byte must still precede each data byte (as described for the serial microport), the values of the address fields for these "BRAM-fill" writes are ignored (except for the value 3fh, which designates the BRC register.) Instead, addresses are internally generated by the ZL38001 for each "BRAM-fill" write. Address generation for "BRAM-fill" writes resumes where it left off following any read transaction while bootload mode is enabled. The first 4096 such "BRAM-fill" writes while bootload is enabled will load the memory, but further ones after that are ignored. Following the write of the first 4096 bytes, the program BRAM will be filled. Before bootload mode is disabled, it is recommended that users then read back the value from the signature register (SIG) and compare it to the one supplied by the factory along with the code. Equality verifies that the correct data has been loaded. The signature calculation uses an 8-bit MISR which only incorporates input from "BRAM-fill" writes. Resetting the bootload bit (C2) in the BRC register to 0 (see Register Summary) exits bootload mode, resetting the signature (SIG) register and internal address generator for the next bootload. A hardware reset (RESET=0) similarly returns the ZL38001 to the ready state for the start of a bootload.
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Zarlink Semiconductor Inc.
ZL38001
FUNCTIONAL DESCRIPTION FOR USING THE BOOTABLE RAM
Data Sheet
BOOTLOAD MODE - Microport Access is to bootload RAM (BRAM) R/W W BRC Register Bits C3C2C1C0 X100 W R R Address 3fh (= 1 1 1 1 1 1 b) other than 3fh 1x xxxxb 0x xxxxb Data Writes "data" to BRC reg. - Bootload frozen; BRAM contents are NOT affected. Writes "data" to next byte in BRAM (bootloading.) Reads back "data" = BRC reg value. - Bootload frozen; BRAM contents are NOT affected. Reads back "data" = SIG reg value. - Bootload frozen; BRAM contents are NOT affected.
NON-BOOTLOAD MODE - Microport Access is to device registers (DREGs) BRC Register Bits C3C2C1C0 X000 R/W W (= a5 a4 R (= a5 a4 Address any
a3 a2 a1 a0
Data Writes "data" to corresponding DREG. b) Reads back "data" = corresponding DREG value. b)
any
a3 a2 a1 a0
PROGRAM EXECUTION MODES C3C2C1C0 0000 C3C2C1C0 0100 C3C2C1C0 1000 C3C2C1C0 1100 Execute program in ROM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG reg reseeded to initial (ready) state Execute program in ROM, while bootloading the RAM. - BRAM address counter increments on microport writes (except to 3fh) - SIG reg recalculates signature on microport writes (except to 3fh) Execute program in RAM, bootload mode disabled. - BRAM address counter reset to initial (ready) state. - SIG reg reseeded to initial (ready) state - NOT RECOMMENDED (Execute program in RAM, while bootloading the RAM) Table 6 - Bootload RAM Control (BRC) Register States
Note: bits C1 C0 are reserved, and must be set to zero.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
Once the program has been loaded, to begin execution from RAM, bootload mode must be disabled (BOOT bit, C2=0) and execution from RAM enabled (RAM_ROMb bit, C3=1) by setting the appropriate bits in the BRC register. During the bootload process, however, ROM program execution (RAM_ROMb bit, C3=0) should be selected. See Table 6 for the effect of the BRC register settings on Microport accesses and on program execution. Following program loading and enabling of execution from RAM, it is recommended that users set the software reset bit in the Main Control (MC) register, to ensure that the device updates the default register values to those of the new program in RAM. Note: it is important to use a software reset rather than a hardware (RESET=0) reset, as the latter will return the device to its default settings (which includes execution from program ROM instead of RAM.) To verify which code revision is currently running, users can access the Firmware Revision Code (FRC) register (see Register Summary). This register reflects the identity code (revision number) of the last program to run register initialization (which follows a software or hardware reset.)
COMMAND/ADDRESS e
DATA INPUT/OUTPUT
DATA 1
R/W A0
A1 A2 A3 A4 A5
X
D0 D1 D2 D3 D4 D5 D6 D7
SCLK b
a
CS c
d
a b c d e
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001. The ZL38001: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused
Figure 8 - Serial Microport Timing for Intel Mode 0
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
COMMAND/ADDRESS e
DATA INPUT
DATA 2 Receive DATA 1 Transmit
R/W A5 A4 A3 A2 A1 A0
X
D7 D6 D5 D4 D3 D2 D1 D0 DATA OUTPUT
High Impedance
D7 D6 D5 D4 D3 D2 D1 D0
SCLK b
a
CS c a b c d e
d
This delay is due to internal processor timing and is equal to Tsch time. The delay is transparent to ZL38001. The ZL38001: latches receive data on the rising edge of SCLK outputs transmit data on the falling edge of SCLK The falling edge of CS indicates that a COMMAND/ADDRESS byte will be transmitted from the microprocessor. The subsequent byte is always data followed by CS returning high. A new COMMAND/ADDRESS byte may be loaded only by CS cycling high then low again. The COMMAND/ADDRESS byte contains: 1 bit - Read/Write 6 bits - Addressing Data 1 bit - Unused
Figure 9 - Serial Microport Timing for Motorola Mode 00 or National Microwire
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Zarlink Semiconductor Inc.
ZL38001
Absolute Maximum Ratings* Parameter 1 2 3 4 5 Supply Voltage Input Voltage Output Voltage Swing Continuous Current on any digital pin Storage Temperature Symbol VDD-VSS Vi Vo Ii/o TST -65 Min. -0.5 VSS-0.3 VSS-0.3 Max. 5.0 5.5 5.5 20 150
Data Sheet
Units V V V mA C mW
90 (typ) 6 Package Power Dissipation PD * Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Recommended Operating Conditions - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 Supply Voltage Input High Voltage Input Low Voltage Operating Temperature TA Sym. VDD Min. 2.7 1.4 VSS -40 Typ. 3.3 Max. 3.6 VDD 0.4 +85 Units V V V C
Test Conditions
Echo Return Limits Characteristics 1 2 Acoustic Echo Return Line Echo Return Min. Typ. Max. 0 0 Units dB dB Test Conditions Measured from Rout -> Sin Measured from Sout -> Rin
DC Electrical Characteristics*- Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics Standby Supply Current: 1 2 3 4 5 6 7 8 Operating Supply Current: Input HIGH voltage Input LOW voltage Input leakage current High level output voltage Low level output voltage High impedance leakage Output capacitance Sym. ICC IDD VIH VIL IIH/IIL VOH VOL IOZ Co 1 10 0.8VDD 0.4VDD 10 0.1 0.7VDD 0.3VDD 10 Min. Typ. 3 20 Max. 70 Units A mA V V A V V A pF VIN=VSS to VDD IOH=2.5 mA IOL=5.0 mA VIN=VSS to VDD Conditions/Notes RESET = 0 RESET = 1, clocks active
8 pF 9 Input capacitance Ci Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing. *DC Electrical Characteristics are over recommended temperature and supply voltage.
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
AC Electrical Characteristics - Serial Data Interfaces - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 MCLK Frequency BCLK/C4i Clock High BCLK/C4i Clock Low BCLK/C4i Period SSI Enable Strobe to Data Delay (first bit) SSI Data Output Delay (excluding first bit) SSI Output Active to High Impedance SSI Enable Strobe Signal Setup SSI Enable Strobe Signal Hold SSI Data Input Setup SSI Data Input Hold ST-BUS/GCI F0i Setup ST-BUS/GCI F0i Hold ST-BUS/GCI Data Output delay ST-BUS/GCI Output Active to High Impedance ST-BUS/GCI Data Input Hold time ST-BUS/GCI Data Input Setup time Sym. fCLK tBCH, tC4H tBLL, tC4L tBCP tSD tDD tAHZ tSSS tSSH tDIS tDIH tF0iS tF0iH tDSD tASHZ tDSH tDSS Min. 19.15 90 90 240 80 80 80 10 15 10 15 20 20 80 80 20 20 150 150 tBCP -15 tBCP -10 7900 Typ. Max. 20.5 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF CL = 150 pF Test Notes
Timing is over recommended temperature and power supply voltages.
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Zarlink Semiconductor Inc.
ZL38001
AC Electrical Characteristics - Microport Timing Characteristics 1 2 3 4 5 6 7 8 9 10 Input Data Setup Input Data Hold Output Data Delay Serial Clock Period SCLK Pulse Width High SCLK Pulse Width Low CS Setup-Intel CS Setup-Motorola CS Hold CS to Output High Impedance Sym. tIDS tIDH tODD tSCP tSCH tSCL tCSSI tCSSM tCSH tOHZ Min. 30 30 100 500 250 250 200 100 100 100 Typ. Max. Units ns ns ns ns ns ns ns ns ns ns CL = 150 pF CL = 150 pF
Data Sheet
Test Notes
Timing is over recommended temperature range and recommended power supply voltages.
Characteristic CMOS reference level Input HIGH level Input LOW level Rise/Fall HIGH measurement point Rise/Fall LOW measurement point
Symbol VCT VH VL VHM VLM
CMOS Level 0.5*VDD 0.9*VDD 0.1*VDD 0.7*VDD 0.3*VDD
Units V V V V V
Table 7 - Reference Level Definition for Timing Measurements
T=1/fCLK MCLK (I)
VH VL
VCT
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 10 - Master Clock - MCLK
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Zarlink Semiconductor Inc.
ZL38001
Bit 7 Sout/Rout (O) tDSD C4i (I)
VH VL
Data Sheet
Bit 6 VCT tC4H tASHZ
VCT tF0iS tF0iH
input sampled
tC4L VCT
F0i (I)
VH VL
start of frame
tDSS tDSH VCT Bit 7 Bit 6
Rin/Sin (I)
VH VL
Figure 11 - GCI Data Port Timing
Bit 7 Sout/Rout (O) tDSD C4i (I)
VH
input sampled
Bit 6 VCT tC4H tASHZ
VL
VCT tC4L
tF0iS tF0iH F0i (I)
VH VL
start of frame
VCT tDSS tDSH VCT Bit 7 Bit 6
Rin/Sin (I)
VH VL
Figure 12 - ST-BUS Data Port Timing
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Zarlink Semiconductor Inc.
ZL38001
Bit 7 Sout/Rout (O) tSD BCLK (I)
VH
input sampled
Data Sheet
Bit 6
Bit 5 VCT
tDD
tBCH
tAHZ VCT
VL
tSSS ENA1 (I) or ENA2 (I)
VH VL
tBCP
tBCL
tSSH VCT
tDIS tDIH
start of frame
VH
Rin/Sin (1)
VL
VCT Bit 7 Bit 6 Bit 5 (see Table 8 for symbol definitions)
Notes: O. CMOS output
I. CMOS input (5 V tolerant)
Figure 13 - SSI Data Port Timing
DATA INPUT DATA1
(I,O)
DATA OUTPUT VCT
tIDS tIDH SCLK (I)
VH VL
tSCH
tODD
tOHZ VCT
tCSSI CS (I)
VH VL
tSCL
tSCP
tCSH VCT
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 14 - INTEL Serial Microport Timing
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
DATA2 (I) (Input)
VH VL
VCT tIDS tIDH tSCH tSCP VCT tCSSM tSCL tCSH VCT tODD tOHZ VCT
SCLK (I)
VH VL
CS (I)
VH VL
DATA1 (O) (Output)
Notes: O. CMOS output I. CMOS input (5 V tolerant) (see Table 8 for symbol definitions)
Figure 15 - Motorola Serial Microport Timing
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Zarlink Semiconductor Inc.
ZL38001
5.0 Register Summary
External Read/Write Address: 00H Reset Value: 00H
7
LIMIT
Data Sheet
6
MUTE_R
5
MUTE_S
4
BYPASS
3
NB-
2
AGC-
1
AH-
0
RESET
Bit 7
Name LIMIT
Description When high, the 2-bit shift mode is enabled in conjunction with bit 7 of LEC register and when low 2-bit shift mode is disabled. Default limit for Rin and Sin is 3.14 dBm0. When high, the Rin path is muted to quite code (after the NLP) and when low the Rin path is not muted. When high, the Sin path is muted to quite code (after the NLP) and when low the Sin path is not muted. When high, the Send and Receive paths are transparently by-passed from input to output and when low the Send and Receive paths are not bypassed. When high, Narrowband signal detectors in Rin and Sin paths are disabled and when low the signal detectors are enabled. When high, AGC is disabled and when low AGC is enabled. When high, the Howling detector is disabled and when low the Howling detector is enabled. When high, the power initialization routine is executed presetting all registers to default values. This bit automatically clears itself to '0' when reset is complete. Register Table 1 - Main Control Register (MC)
6 5 4 3 2 1 0
MUTE_R MUTE_S BYPASS NBAGCAHRESET
External Read/Write Address:21H Reset Value: 00H
7
P-
6
ASC-
5
NLP-
4
INJ-
3
HPF-
2
HCLR
1
ADAPT-
0
ECBY
Bit 7 6 5
Name PASCNLP-
Description When high, the Exponential weighting function for the adaptive filter is disabled and when low the weighting function is enabled When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled. When high, the Non Linear Processor is disabled in the Sin/Sout path and when low the NLP is enabled.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC)
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Zarlink Semiconductor Inc.
ZL38001
External Read/Write Address:21H Reset Value: 00H
7
P-
Data Sheet
6
ASC-
5
NLP-
4
INJ-
3
HPF-
2
HCLR
1
ADAPT-
0
ECBY
Bit 4 3 2 1 0
Name INJHPFHCLR ADAPTECBY
Description When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled. When high, Offset nulling filter is bypassed in the Sin/Sout path and when low the Offset nulling filter in not bypassed. When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled. When high, the Echo estimate from the filter is not subtracted from the input (Sin), when low the estimate is subtracted.
Register Table 2 - Acoustic Echo Canceller Control Register (AEC) (continued)
External Read/Write Address: 01H Reset Value: 00H
7
SHFT
6
ASC-
5
NLP-
4
INJ-
3
HPF-
2
HCLR
1
ADAPT-
0
ECBY
Bit 7
Name SHFT
Description When high the 16-bit linear mode, inputs Sin, Rin, are shift right by 2 and outputs Sout, Rout are shift left by 2. This bit is ignored when 16-bit linear mode is not selected in both ports. This bit is also ignored if bit 7 of MC register is set to zero. When high, the Internal Adaptation speed control is disabled and when low the Adaptation speed is enabled. When high, the Non Linear Processor is disabled in the Rin/Rout path and when low the NLP is enabled. When high, the Noise filtering process is disabled in the NLP and when low the Noise filtering process is enabled. When high, Offset nulling filter is bypassed in the Rin/Rout path and when low the Offset nulling filter in not bypassed. When high, Adaptive filter coefficients are cleared and when low the filter coefficients are not cleared.
6 5 4 3 2
ASCNLPINJHPFHCLR
Register Table 3 - Line Echo Canceller Control Register (LEC)
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Zarlink Semiconductor Inc.
ZL38001
External Read/Write Address: 01H Reset Value: 00H
7
SHFT
Data Sheet
6
ASC-
5
NLP-
4
INJ-
3
HPF-
2
HCLR
1
ADAPT-
0
ECBY
Bit 1 0
Name ADAPTECBY
Description When high, the Echo canceller adaptation is disabled and when low the adaptation is enabled. When high, the Echo estimate from the filter is not substracted from the input (Rin), when low the estimate is substracted.
Register Table 3 - Line Echo Canceller Control Register (LEC) (continued)
External Read Address: 22H Reset Value: 00H
7
-
6
ACMUND
5
HWLNG
4
-
3
NLPDC
2
DT
1
NB
0
NBS
Bit 7 6 5 4 3 2 1 0
Name ACMUND HWLNG NLPDC DT NB NBS RESERVED.
Description
When low, No active signal in the Rin/Rout path. When high, Howling is occurring in the loop and when low, no Howling is detected. RESERVED. When high, the NLP is activated and when low the NLP is not activated. When high the Double Talk is detected and when low, the Double talk is not detected. LOGICAL OR of the status bit NBS + NBR from LSR Register. When high, the Narrowband signal has been detected in the Sin/Sout path and when low, the Narrowband signal has not been detected in the Sin/Sout path.
Register Table 4 - Acoustic Echo Canceller Status Register (ASR) (* Do not write to this register)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 02H Reset Value: 00H
7 6 5 4 3 2 1 0
Bit 7 6 5 4 3 2 1 0
Name NLPC DT NB NBR RESERVED.
Description
When high, NLP is activated and when low NLP is not activated. When high, double-talk is detected and when low double-talk is not detected. This bit indicates a LOGICAL-OR of Status bits NBR + NBS (from ASR Register). When high, a narrowband signal has been detected in the Receive (Rin) path. When low no narrowband signal is not detected in the Rin path.
Register Table 5 - Line Echo Canceller Status Register (LSR) (* Do not write to this register)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address:20H Reset Value: 6DH
7
-
6
-
5
-
4
G4
3
G3
2
G2
1
G1
0
G0
Bit 7 6 5 4-0
Name Reserved Reserved Reserved G4-0 Must keep as Logic 0. Must keep as Logic 1. Must keep as Logic 1.
Description
User Gain Control on the Rin/Rout path (Tolerance of gains: +/- 0.15 dB). The hexadecimal number represents G3 to G0 value in the table below.
Register Value 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh Gain -24 dB -21 dB -18 dB -15 dB -12 dB -9 dB -6 dB -3 dB 0 dB +3 dB +6 dB +9 dB +12 dB +15 dB +18 dB +21 dB Register Value 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh Gain +24 dB +27 dB +30 dB +33 dB +36 dB +39 dB +42 dB +45 dB +48 dB Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Register Table 6 - Receive Gain Control Register
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address: 32H Reset Value: 25H
7
HG2
6
HG1
5
HG0
4
DTGain
3
-
2
-
1
-
0
-
Bit 7 6 5 4
Name DTRGain RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 1.
Description
This bit controls the gain level at Rout during double talk. When this bit is high 12 dB of attenuation is injected into the Rout path during double talk. When this bit is low the gain pad is disabled. RESERVED. Must keep as 0. RESERVED. Must keep as 1. RESERVED. Must keep as 0. RESERVED. Must keep as 1.
3 2 1 0
-
Register Table 7 - Double Talk Gain Control Register 1 (DTGCR1)
External Read/Write Address: 12H Reset Value: 00H
7
-
6
-
5
-
4
DTSGain
3
2
-
1
-
0
Bit 7 6 5 4
Name DTSGain RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 0.
Description
This bit controls the gain level at Sout during double talk. When this bit is high 12 dB of attenuation is injected into the Sout path during double talk. When this bit is low the gain pad is disabled. RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 0.
3 2 1 0
-
Register Table 8 - Double Talk Gain Control Register 2 (DTGCR2)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read/Write Address: 31H Reset Value: 21H
7
DTDT2
6
DTDT1
5
DTDT0
4
-
3
-
2
-
1
-
0
-
Bit 7 6 5
Name DTDT2 DTDT1 DTDT0
DTDT2, DTDT1, DTDT0 Value 000 001 010 011
Description
DTDT -12 dB -6 dB 0 dB +6 dB
DTDT2, DTDT1, DTDT0 Value 100 101 110 111
DTDT +12 dB +18 dB +24 dB +30 dB
4 3 2 1 0
-
RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 0. RESERVED. Must keep as 1.
Register Table 9 - Double Talk detection Threshold Register (DTDT)
External Read Address: 16H Reset Value: 00H
7
RIPD7
6
RIPD6
5
RIPD5
4
RIPD4
3
RIPD3
2
RIPD2
1
RIPD1
0
RIPD0
Bit 7 6 5 4 3 2 1 0
Name RIPD7 RIPD6 RIPD5 RIPD4 RIPD3 RIPD2 RIPD1 RIPD0
Description These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see Figure 1). The information is in 16bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 10 - Receive (Rin) Peak Detect Register 1 (RIPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 17H Reset Value: 00H
7
RIPD15
6
RIPD14
5
RIPD13
4
RIPD12
3
RIPD11
2
RIPD10
1
RIPD9
0
RIPD8
Bit 7 6 5 4 3 2 1 0
Name RIPD15 RIPD14 RIPD13 RIPD12 RIPD11 RIPD10 RIPD9 RIPD8
Description These peak detector registers allow the user to monitor the receive in signal (Rin) peak level at reference point R1 (see Figure 1). The information is in 16bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 11 - Receive (Rin) Peak Detect Register 2 (RIPD2)
External Read Address: 18H Reset Value: 00H
7
REPD7
6
REPD6
5
REPD5
4
REPD4
3
REPD3
2
REPD2
1
REPD1
0
REPD0
Bit 7 6 5 4 3 2 1 0
Name REPD7 REPD6 REPD5 REPD4 REPD3 REPD2 REPD1 REPD0
Description These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 12 - Receive (Rin) ERROR Peak Detect Register 1 (REPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 19H Reset Value: 00H
7
REPD15
6
REPD14
5
REPD13
4
REPD12
3
REPD11
2
REPD10
1
REPD9
0
REPD8
Bit 7 6 5 4 3 2 1 0
Name REPD15 REPD14 REPD13 REPD12 REPD11 REPD10 REPD9 REPD8
Description These peak detector registers allow the user to monitor the error signal peak level at reference point R2 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 13 - Receive (Rin) ERROR Peak Detect Register 2 (REPD2)
External Read Address: 3AH Reset Value: 00H
7
ROPD7
6
ROPD6
5
ROPD5
4
ROPD4
3
ROPD3
2
ROPD2
1
ROPD1
0
ROPD0
Bit 7 6 5 4 3 2 1 0
Name ROPD7 ROPD6 ROPD5 ROPD4 ROPD3 ROPD2 ROPD1 ROPD0
Description These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 14 - Receive (Rout) Peak Detect Register 1 (ROPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 3BH Reset Value: 00H
7
ROPD15
6
ROPD14
5
ROPD13
4
ROPD12
3
ROPD11
2
ROPD10
1
ROPD9
0
ROPD8
Bit 7 6 5 4 3 2 1 0
Name ROPD15 ROPD14 ROPD13 ROPD12 ROPD11 ROPD10 ROPD9 ROPD8
Description These peak detector registers allow the user to monitor the receive out signal (Rout) peak level at reference point R3 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 15 - Receive (Rout) Peak Detect Register 2 (ROPD2)
External Read Address: 36H Reset Value: 00H
7
SIPD7
6
SIPD6
5
SIPD5
4
SIPD4
3
SIPD3
2
SIPD2
1
SIPD1
0
SIPD0
Bit 7 6 5 4 3 2 1 0
Name SIPD7 SIPD6 SIPD5 SIPD4 SIPD3 SIPD2 SIPD1 SIPD0
Description These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see Figure 1). The information is in 16bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 16 - Send (Sin) Peak Detect Register 1 (SIPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 37H Reset Value: 00H
7
SIPD15
6
SIPD14
5
SIPD13
4
SIPD12
3
SIPD11
2
SIPD10
1
SIPD9
0
SIPD8
Bit 7 6 5 4 3 2 1 0
Name SIPD15 SIPD14 SIPD113 SIPD12 SIPD11 SIPD10 SIPD9 SIPD8
Description These peak detector registers allow the user to monitor the receive in signal (Sin) peak level at reference point S1 (see Figure 1). The information is in 16bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 17 - Send (Sin) Peak Detect Register 2 (SIPD2)
External Read Address: 38H Reset Value: 00H
7
SEPD7
6
SEPD6
5
SEPD5
4
SEPD4
3
SEPD3
2
SEPD2
1
SEPD1
0
SEPD0
Bit 7 6 5 4 3 2 1 0
Name SEPD7 SEPD6 SEPD5 SEPD4 SEPD3 SEPD2 SEPD1 SEPD0
Description These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 18 - Send ERROR Peak Detect Register 1 (SEPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 39H Reset Value: 00H
7
SEPD15
6
SEPD14
5
SEPD13
4
SEPD12
3
SEPD11
2
SEPD10
1
SEPD9
0
SEPD8
Bit 7 6 5 4 3 2 1 0
Name SEPD15 SEPD14 SEPD13 SEPD12 SEPD11 SEPD10 SEPD9 SEPD8
Description These peak detector registers allow the user to monitor the error signal peak level in the send path at reference point S2 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 19 - Send ERROR Peak Detect Register 2 (SEPD2)
External Read Address: 1AH Reset Value: 00H
7
SOPD7
6
SOPD6
5
SOPD5
4
SOPD4
3
SOPD3
2
SOPD2
1
SOPD1
0
SOPD0
Bit 7 6 5 4 3 2 1 0
Name SOPD7 SOPD6 SOPD5 SOPD4 SOPD3 SOPD2 SOPD1 SOPD0
Description These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 20 - Send (Sout) Peak Detect Register 1 (SOPD1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 1BH Reset Value: 00H
7
SOPD15
6
SOPD14
5
SOPD13
4
SOPD12
3
SOPD11
2
SOPD10
1
SOPD9
0
SOPD8
Bit 7 6 5 4 3 2 1 0
Name SOPD15 SOPD14 SOPD13 SOPD12 SOPD11 SOPD10 SOPD9 SOPD8
Description These peak detector registers allow the user to monitor the Send out signal (Sout) peak level at reference point S3 (see Figure 1). The information is in 16-bit 2's complement linear coded format presented in two 8-bit registers. The high byte is in Register 2 and the low byte is in Register 1.
Register Table 21 - Send (Sout) Peak Detect Register 2 (SOPD2)
External Read Address: 24H Reset Value: 80H
7
L0
6
-
5
-
4
-
3
-
2
-
1
-
0
-
Bit 7 6 5 4 3 2 1 0
Name L0 -
Description This bit is used in conjunction with Rout Limiter Register 2. (See description below.) RESERVED
Register Table 22 - Rout Limiter Register 1 (RL1)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 25H Reset Value: 3EH
7
L8
6
L7
5
L6
4
L5
3
L4
2
L3
1
L2
0
L1
Bit 7 6 5 4 3 2 1 0
Name L8 L7 L6 L5 L4 L3 L2 L1
Description In conjunction with bit 7 (L0) of the above (RL1) register, this register (RL2) allows the user to program the output Limiter threshold value in the Rout path. Default value is (07D)h which is equal to 3.14 dBmo Maximum value is (1FF)h = 15 dBmo Minimum value is (001)h = -38 dBmo
Register Table 23 - Rout Limiter Register 2 (RL2)
External Read Address: 26H Reset Value: 3DH
7
L4
6
L3
5
L2
4
L1
3
L0
2
1
0
Bit 7 6 5 4 3 2 1 0
Name L4 L3 L2 L1 L0 -
Description This register allows the user to program the output Limiter threshold value in the Rout path. Default value is (1D)h which is equal to 3.14 dBmo Maximum value is (1F)h
RESERVED. Must be keep as 1. RESERVED. Must be keep as 0. RESERVED. Must be keep as 1. Register Table 24 - Sout Limiter Register (SL)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 03H Reset Value: 00H
7
FRC2
6
FRC1
5
FRC0
4
-
3
-
2
-
1
-
0
-
Bit 7 6 5 4 3 2 1 0
Name FRC2 FRC1 FRC0 RESERVED
Description Revision code of the firmware program currently being run (default=rom=00).
Register Table 25 - Firmware Revision Code Register (FRC)
External Read Address: 3FH Reset Value: 00H
7
-
6
-
5
-
4
-
3
2
1
0
C3
C2 Description
C1
C0
Bit 7 6 5 4 3 2 1 0
Name C3 C2 C1 C0 RESERVED
RAM_ROMb bit. When high, device executes from RAM. When low, device executes from ROM. BOOT bit. When high, puts device in bootload mode. When low, bootload is disabled. RESERVED. Must be set to zero. RESERVED. Must be set to zero. Register Table 26 - Bootload RAM Control Register (BRC)
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Zarlink Semiconductor Inc.
ZL38001
Data Sheet
External Read Address: 07H Reset Value: 10H
7
SIG7
6
SIG6
5
SIG5
4
SIG4
3
SIG3
2
SIG2
1
SIG1
0
SIG0
Bit 7 6 5 4 3 2 1 0
Name SIG7 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0
Description This register provides the signature of the bootloaded data to verify error-free delivery into the device. Note: this register is only accessible if BOOT bit is high (bootload mode enabled) in the above BRC register. While bootload is disabled, the register value is held constant at its reset seed value of FFh.
Register Table 27 - Bootload RAM Signature Register (SIG)
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Zarlink Semiconductor Inc.
c Zarlink Semiconductor 2004. All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
c Zarlink Semiconductor 2003 All rights reserved.
Package Code Previous package codes
ISSUE ACN DATE APPRD.
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